Phase locked loop-(PLL) based frequency synthesizers are widely used in communication applications such as wireless communication, Bluetooth, wireless local area network (WLAN), Wideband Code-Division and Multiple Access (WCDMA). PLL-based frequency synthesizers (frequency synthesizers) operate to lock on to an incoming reference signal in order to generate an output signal having a frequency that is related to that of the incoming reference signal. PLL-based frequency synthesizer typically uses frequency divider circuits to generate output frequencies that can be expressed as the product between the frequency of the incoming reference signal and the ratio of two integers N and M, e.g, fOUT=(N/M)*fREF. The direct multiplication technique used in this type of frequency synthesizers requires tradeoff between the ratio of N and M and the noise performance of the frequency synthesizer. Increasing the values of N and M to achieve fine frequency resolution worsens the phase jitter performance in the output signal by a factor of the logarithm of N and M. In addition, increasing the values of N and M by adding more bits causes power dissipation and increased die size.
To overcome the above problems caused by integer multiplication in frequency synthesizers, fractional-N frequency synthesizers can be used. In fractional-N frequency synthesizers, a non-integer number is used to multiply the frequency of the incoming reference signal. The time average of the target non-integer number is achieved by dividing the frequency of the reference signal by N or by N+1 alternatively. For example, fractional-N frequency synthesizer divided by 19.1 consists of N-divider dividing nineteen 90% of the time, and by twenty 10% of the time. However, fractional-N frequency synthesizers introduce jitter noise in the output signal due to the phase error accumulated in each cycle.
To improve jitter noise in fractional-N frequency synthesizers, a sigma delta modulator can be used to shape the noise imported by the average division method. However, the heavy digital activity of the sigma delta modulator, which provides the averaging function, creates spurious components at the output. In particular, by using the average division of sigma delta modulators, the average division is correct, but the instantaneous division is incorrect. Because of this, the phase frequency detector and charge pump are constantly trying to correct for instantaneous phase errors. In addition, an overflow from the sigma delta modulator creates a resulting phase step at the phase frequency detector that cannot be filtered by the loop low pass filter. This phase step causes jitter at the output signal. In addition, the digital noise, combined with inaccuracies in matching the hard-working charge pump, results in spurious levels greater than those allowable by many communications standards.
In one prior art method, a variable delay is added in the feedback loop of the frequency synthesizers to remove the resulting phase step at the phase frequency detector. This method reduces this type of jitter at the output of the frequency synthesizer. However, this type of frequency synthesizer has “dead zone” problems that result from the small amount of phase error that cannot be detected by the phase frequency detector. This causes large jitter and phase noise in the output signal. In addition, adding a phase delay in the feedback loop of a PLL-based frequency synthesizer adds complexity in the system that adversely affects the size and noise performance the frequency synthesizer.
Thus, there is a need for a high speed PLL-based frequency synthesizer that can produce an output frequency that is a fractional multiplication of the input frequency that has good jitter noise performance. Furthermore, there is a need for a low jitter frequency synthesizer that has good jitter noise performance. The present invention meets the above needs.